Applications

Semiconductors

Electrostatic chucks

Thermal design

We apply surrogate-based design optimization to an electrostatic chuck for semiconductor manufacturing. Improving wafer-temperature uniformity requires spatial predictions, but high-fidelity thermal-flow simulations limit the amount of training data available for repeated design evaluations.

Learning temperature fields from multiple fidelities

The surrogate projects high- and low-fidelity temperature fields onto a shared POD basis, then predicts the reduced coordinates with multifidelity kriging. In the reported design comparison, it improves all evaluated thermal quantities while using 20% less data-generation cost than the high-fidelity-only surrogate approach, demonstrating the value of combining simulation fidelities.

Paper: Wang et al. [1]

Reference and representative optimal electrostatic-chuck wafer-temperature fields, with the temperature changes in the outer hot region, inner cold region, and coolant-inlet cold spot marked.
A representative optimized design redistributes the wafer temperature field to improve uniformity. [1]
Major components of a capacitively coupled plasma etcher, a 3D electrostatic-chuck assembly, the coolant path, and surface emboss structure with seven design variables marked.
Electrostatic-chuck visualizations identify the seven design variables across the plasma chamber, 3D assembly, coolant path, and surface emboss structure. [1]
Original wafer-temperature field and low-, high-, and multi-fidelity surrogate predictions with their corresponding prediction errors.
For a representative test design, the multi-fidelity surrogate combines 60 high-fidelity and 100 low-fidelity samples; its field prediction is compared with high-fidelity-only (80 samples) and low-fidelity-only (400 samples) surrogates. [1]

Optimization problem

Optimization formulation
Formulation element Electrostatic-chuck thermal design
CaseElectrostatic-chuck thermal design
ObjectiveMinimize temperature uniformity, 3σT.
Design variables
Inner-zone emboss contact ratio 1
Outer-zone emboss contact ratio 1
Inner coolant-path height 1
Outer coolant-path height 1
Inner coolant-path width 1
Outer coolant-path width 1
Outer coolant-path fin height 1
Total design variables7
Constraints
Mean temperature (μT ≤ 17 °C) 1
Maximum temperature (max(T) ≤ 21.5 °C) 1
Inner contact ratio no greater than outer ratio (CR1 ≤ CR2) 1
Sum of contact ratios (CR1 + CR2 ≤ 10) 1
Outer coolant-path width no greater than inner width (W2 ≤ W1) 1
Fin-height feasibility (F1 ≤ W2 − 2) 1
Total constraints6
Models and conditionsHigh-fidelity Ansys Fluent dynamic heat-transfer CFD with SST k-ω turbulence; low-fidelity Ansys Mechanical steady-state heat transfer; POD and multifidelity kriging predict the wafer-temperature field.
Representative sourceDesign Optimization of Semiconductor Manufacturing Equipment Using a Novel Multi-Fidelity Surrogate Modeling Approach
Source locatorTable 1, PDF page 6.

References

  1. Bingran Wang, Min Sung Kim, Taewoong Yoon, Dasom Lee, Byeong-Sang Kim, Dougyong Sung, John T. Hwang. Design Optimization of Semiconductor Manufacturing Equipment Using a Novel Multi-Fidelity Surrogate Modeling Approach. Optimization and Engineering, 27(2), 1451–1479, 2026.
    PDF

Research connections

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